1. Field of the Invention
The present invention relates to a semiconductor apparatus, more particularly, the present invention relates to the semiconductor apparatus which prevents generating noise and being influenced by noise.
2. Description of the Related Art
As an example of a conventional semiconductor apparatus which inputs and outputs data and has a clock terminal, a DRAM having a clock terminal is explained.
FIG. 1 is a block diagram showing a configuration of a conventional DRAM. In FIG. 1, the configuration related to the clock signal is shown. DRAM101 includes a clock input buffer 103, DRAM core 104, DQ output unit 105 and DLL(Delayed Locked Loop)106.
The clock input buffer 103 receives an external clock signal being transmissible from outside DRAM101. Then, it outputs the external clock signal just as it is (or being amplified) to DRAM core 104 and DLL1O6 as an internal clock signal.
DRAM core 104 operates data processing such as the data reading, the data writing, the data deleting and the like based on the internal clock signal. Especially, while operating the data reading, it outputs an output signal (the reading data) to DQ output unit 105 as a DQ signal.
DLL106 delays the internal clock signal for the certain delay time based on the internal clock signal. DLL106 outputs the delayed internal clock signal to DQ output unit 105 as the internal clock signal.
DQ output unit 105 outputs DQ signal outside DRAM101 in the timing of the internal clock signal which was output from DLL106.
A DQ terminal which is an output terminal and outputs DQ signal from DRAM101 is in the position near a CLK terminal which is an input terminal and inputs the external clock signal to DRAM101. Therefore, when DRAM101 reads data, the cross talk sometimes occurs between the DQ terminal (or the neighborhood) and the CLK terminal (or the neighborhood). In this case, receiving the same phase component cross talk noise of the DQ signal in data reading, the timing noise of the external clock signal inputted to DRAM101 becomes big.
Hence, the technique not to be influenced by the noise based on a clock signal supplied from outside is desired for a semiconductor apparatus having a clock terminal. The technique which restrains the influence of the cross talk between the data output signal outputted to outside and the clock signal inputted from outside is desired for a semiconductor apparatus having a clock terminal.
Related Art titled “a refresh circuit and a control circuit of an optical disc playback apparatus using thereof” is disclosed in Japanese Laid Open Patent Application (JP-A-2000-260179).
The refresh circuit of this related art has a standard clock generating circuit and a refresh signal generating circuit. The standard clock generating circuit has an oscillator and a phase locked loop. The oscillator outputs a reference clock having predetermined frequency. The phase locked loop outputs the standard clock having a predetermined frequency based on the reference clock. The refresh signal generating circuit generates the refresh signal of the dynamic RAM based on the standard clock. The oscillator stops oscillation according to the stop signal. The stop signal is generated at the time of the sleep mode. In the sleep mode, data processing is stopped temporarily in the condition not to cut a power supply in. The standard clock generating circuit generates a sleep mode clock. The sleep mode clock has a period which the dynamic RAM needs at the time of the sleep mode. The refresh signal generating circuit generates the refresh signal of the dynamic RAM according to the sleep mode clock at the time of the sleep mode. The phase locked loop may be composed so as to carry out a self-excited oscillation while the reference clock isn't inputted. The standard clock generating circuit may further have a frequency transfer circuit. The frequency transfer circuit transfers a frequency of the self-excited oscillation of the phase locked loop and generates a clock at the time of the sleep while the stop signal is inputted.
The object of this related art is to provide a refresh circuit which reduces consumption of electric power while it maintains data in a DRAM when stopping data processing temporarily in a sleep mode.
Related Art titled “method and apparatus for reproducing information by varying a sensitivity of a phase-locked loop in accordance with a detection state of a reproduced signal” is disclosed in U.S. Pat. No. 4,974,221.
The information reproducing apparatus includes: means for reproducing a signal from an information recording medium; a phase locked loop circuit; drop detection means; holding means; and means for varying the sensitivity level of the phase locked loop.
The phase locked loop circuit produces a clock signal from the reproduced signal, the phase locked loop circuit having a sensitivity level. The drop detection means detects a drop in the reproduced signal, wherein the phase locked loop circuit has a first sensitivity level prior to a drop in the reproduced signal. The holding means holds the frequency and phase of the clock signal when the reproduced signal drops and releasing means for releasing the hold when the reproduced signal recovers. The means varies the sensitivity level of the phase locked loop such that the sensitivity level is lower than the first level immediately after the hold for the clock signal has been released by the releasing means and the sensitivity is raised to the first sensitivity level when a residual phase error of the phase locked loop is within a predetermined error range.
It is an object of this technique to provide an apparatus for reproducing information which prevent synchronization of a PLL circuit when frequency and phase of a reproduced signal are varied by jitter and when the reproduced signal drops and recovers due to a defect on a recording medium, such as a scratch and dust.
Related Art titled “a PLL circuit, a control apparatus of a PLL circuit and a disc apparatus” is disclosed in Japanese Laid Open Patent Application (JP-A-2000-173194).
The PLL circuit of this related art includes a phase comparator, a charge pump, a lowpass filter, a voltage control oscillator, a divider, a period information generation circuit and a control circuit. The phase comparator compares a phase of the standard signal and a feedback signal and outputs a phase difference signal. The charge pump generates charge pump output based on the phase difference signal. The lowpass filter smoothes the charge pump output and outputs control voltage. The voltage control oscillator generates output signal of a frequency based on the control voltage. The divider divides the output signal of the voltage control oscillator and generates a feedback signal. The period information generating circuit generates period information based on the output signal of the voltage control oscillator. The period information shows a certain period which contains the time to expect that the standard signal comes next about. The control circuit refers to the period information and detects that a standard signal came in the period. Then, based on the signal of the phase difference between the standard signal and the feedback signal, it controls the output of the voltage control oscillator. Also, the control circuit makes maintain a predetermined period when the standard signal didn't come in the period.
The object of this related art is to provide the PLL circuit which can generate an output signal normally even though noise is contained in a standard signal and pulses of the standard signal is lacked.
Related Art titled “a PLL circuit” is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 5-114857).
The PLL circuit of the technique includes a crystal oscillator, a 1st divider, a voltage control oscillator, a 2nd divider, a phase comparator, a lock condition storage circuit and a lock condition reappearance circuit. The crystal oscillator is used to get a base oscillation. The 1st divider is used to divide an output of the crystal oscillator. The voltage control oscillator is used to get an output signal which has an oscillation frequency based on given control voltage. The 2nd divider is used to divide the output signal of the voltage control oscillator. The phase comparator detects a phase error of the output signal of the 2nd divider based on the output signal of the 1st divider. Then, the phase comparator is used to give control voltage according to the phase error to the voltage control oscillator. The lock condition storage circuit is used to maintain a value of the control voltage to the voltage control oscillator at the time that the frequency is locked. The lock condition reappearance circuit is used to receive the control signal and supply the control voltage of the received value to the voltage control oscillator in case that the frequency is unlocked. The lock condition storage circuit maintains the value of the control voltage.
The object of the technique is to provide a PLL circuit which reduces lockup time, suppressing the change of control voltage to the voltage control oscillator in case that a frequency is unlocked.